Performance Implication of Hashed Page Tables on ARM System Memory Management Unit Design

Ahstract-The rise of artificial intelligence and machine learning applications has increased demands for both computing resources and memory in edge consumer devices. Consequently, the SoC architectures within these devices are adopting het-erogeneous structures to meet these emerging demands. This trend has led to extensive research on IOMMUs, such as ARM releasing SMMU v3.3. However, unlike traditional MMUs in CPUs designed for single-process execution, IOMMUs must handle configuration lookups in addition to simple translation lookups to support multiple devices simultaneously. Therefore, this exacerbates the complexity of the address translation lookups associated with the multi-level page table structure and compli-cates the design of caches such as TLBs. This paper studies the ARM SMMU architecture, focusing on the performance implications of integrating hashed page tables to simplify the translation lookups in SMMUs and thereby, improve SMMU performance. Our findings suggest that hashed page tables holds the potential to enhance the scalability and efficiency of SMMUs in heterogeneous SoC environments.