A Low-Area Phase-Locked Loop with 50% Duty-Cycle for 2.4-GHz WPT Beamforming System in Biomedical Application

This paper presents a phase-locked loop (PLL) for a 2.4 GHz wireless power transfer (WPT) beamforming system designed in a 0.18-μm CMOS process. Due to the characteristics of the beamforming system, the power transfer is not proper unless the duty cycle is less than 50%. In addition, a large number of power amplifiers (PA) are required in the Tx part, so the design should be low-area except for the PA array to reduce the total size. We designed a voltage controlled-negative skewed ring oscillator (VC-NSRO) based on a ring oscillator with a true single-phase clock (TSPC) frequency divider, eliminating the use of a large-area LC oscillator, to achieve stable operation at frequencies exceeding twice 2.4 GHz while maintaining a duty cycle of 50%. The PLL core active area is 210 × 160 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, the phase noise of the overall PLL is -85.43 dBc/Hz at 1 MHz offset, and the lock time is 53 μs.