Mitigating SAT Attack in IPs through Modified Weighted Logic Locking

Today’s VLSI hardware and IP from third parties are vulnerable to several attacks, thereby companies security. The split manufacturing techniques evolved in market leads to the IP piracy issues. Logic locking is one of the promising method of resisting IP piracy and related issues. Hardware security modules are employed in ICs to lock the functionality of the IC from theft and to protect ICs from attacks. This paper focuses on the various methods of attacking strategies and developing a new methodology of preventing the attacks with high output corruption. This paper mainly aims to enhance the weighted logic locking against powerful attack called SAT attack. So that it can offer high output corruption with strong security for the intellectual property. Further the proposed methodology incurs very less in increase in area and power, this highlights the lightweight nature of this scheme.