High-Speed Design Approaches for CCSDS LDPC Encoder Systems

In this paper, the implementation of a QC-LDPC encoder using AR4JA photograph LDPC is presented. This design utilizes a block-cyclic generator matrix from a quasi-cyclic parity check matrix to reduce encoder complexity. Additionally, an increase in speed of 22.87 % and a reduction in resource utilization of 14.28 % is also achieved through this method. The synthesis report of the utilization summary and delay from Vivado is shown and compared with an efficient QC- LDPC encoder using the Richardson Urbanke algorithm. FPGA implementation is also performed for the proposed design.