Comparative Analysis of FinFET and 45nm CMOS Technology in Adder Circuit Performance

The paper presents a comprehensive comparative analysis of the implementations of a 16-transistor full-adder circuit using both 18nm FinFET and 45nm CMOS technologies. The effect of technology scaling on the intrinsic performance parameters of the circuit is analyzed in this study, with critical delay analysis defining overall performance and circuit speed. Designs were developed and simulated using Cadence Virtuoso. The designs were developed and simulated using Cadence Virtuoso. We used the Generic Process Design Kit (GPDK) 45nm and 18nm FinFET technology libraries. For delay and performance variations, transient analysis was performed. In the 45nm CMOS design, the full-adder circuit demonstrated reliable operation with a mean delay of moderate values, thus achieving a balance in power consumption and operational speed useful for a range of applications. On the other hand, the 18nm FinFET realization featured significant delay reductions, superior channel control abilities, and reduced leakage currents. This is specifically attributed to the inherent characteristics of FinFET structures. This makes FinFET a promising technology for low-power, high-speed applications that easily counter all the issues related to typical CMOS scaling. The paper thus focuses on the benefits of using FinFET technology while designing advanced Very Large-Scale Integration (VLSI). This brings significant insight into the optimization of a full-adder circuit that decreases power consumption along with improving processing speeds, thus allowing for more efficient Implementations in future technology nodes.