Utilizing Don't-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits

We propose an exact method of synthesizing Nearest Neighbor Architecture (NNA) compliant networks of CNOT gates on 2-D architecture quantum computers using SMT solvers. To minimize noisy CNOT gates in the circuit, previous methods have employed SMT solvers and partitioning to obtain a lower CNOT gate count than contemporary methods. We observe that there is no need to fix the positions of T-gates relative to the source circuit; we can freely move them relative to the original, in turn enabling the gates that implement the logic feeding into them to be freely placed. In this paper, we introduce a set of constraints based around relaxing the constraints on the logic that acts on the T-gates in the circuit. Using these, we improve both the runtime and the quantum cost of the generated circuits. We compare our method to the method by Ding et al., and find a reduction 29.22% in the runtime and 58.11% in the quantum cost. We also find an advantage vs. IBM's SabreSwap.