Multi-FPGA System for Quantum Error Correction with Lattice Surgery

A practical decoder for quantum error correction must decode a dynamic decoding graph comprising all logical qubits in the system in real-time, a challenging task due to resource limitations. We report HeliosNet, a first-of-its-kind decoding system that overcomes resource constraints through a distributed multi-FPGA architecture. It employs a hybrid treegrid topology to minimize latency for lattice surgery operations distributed across multiple FPGAs. Furthermore, HeliosNet introduces fusion-Union-Find, a novel approach to decoding merged logical qubits that avoids redundant computations associated with traditional window decoders. Additionally, we designed HeliosNet architecture to overcome the IO limitation and minimize data movement latency when integrating with existing quantum control systems. Our exploratory prototype of HeliosNet consists of five Xilinx VMK-180 FPGAs and can decode 100 logical qubits <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(d=5)$</tex> faster than the rate of measurement. Thus, we believe that HeliosNet is a promising candidate for the logical qubit decoding layer in the quantum computer control stack.