Low-Power Half-Flux-Quantum based Counter Circuits for Cryogenic Quantum Computers

The number of bits in quantum computers needs to be increased since large problems must be solved to achieve quantum acceleration. Superconducting qubits are the most advanced qubit devices currently available. A method has been proposed to place a quantum-classical interface on a 4 K stage to ensure scalability. The practical implications of a simple counter circuit in the interface and its role in processing the qubit read results have been demonstrated. A method is needed for configuring a counter circuit with low power consumption to improve scalability. In this paper, we design a novel counter circuit using the Half-Flux Quantum (HFQ) technology. This technology operates in cryogenic environments and has lower power consumption than the Single-Flux Quantum (SFQ) tech-nology. In addition, we conducted a comparative evaluation of circuits dedicated to the NISQ algorithm using SFQ and equivalent circuits implemented using HFQ. Assuming the same power consumption technology applicable to SFQ can be applied to HFQ, we found that the proposed HFQ-based counter circuit can reduce the power consumption by up to 97%.