Power Efficient Baugh Wooley Multiplier Design using Hybrid Lector and Galeor Technique

In digital signal processing (DSP) and high-speed arithmetic circuits, multipliers play a crucial role. The Baugh-Wooley multiplier is a well-known architecture for efficient two's complement multiplication, primarily used in signed number multiplications. However, traditional CMOS-based multipliers' power consumption and leakage current pose challenges for energy-efficient design, especially in low-power and portable applications. This paper proposes an enhanced Baugh-Wooley multiplier architecture using LECTOR (Leakage Control Transistor) and GALEOR (Gated Leakage CMOS) techniques to reduce leakage power and improve energy efficiency. The Baugh-Wooley multiplier is optimized by integrating the LECTOR technique, which uses additional transistors to control the leakage path dynamically, reducing subthreshold leakage during idle periods. Simultaneously, the GALEOR technique is employed to selectively turn off non-critical sections of the multiplier when not in use, minimizing overall power consumption.