Design and Implementation of Inter-Cluster Communication Mechanism for Heterogeneous Multi-Cluster Intelligent System SoC

With advancements in chip manufacturing technology and the increasing demand for workforce in intelligent systems, heterogeneous cluster architecture has emerged as a mainstream approach in System on Chip (SoC) design. Each SoC cluster is tailored to perform specific tasks, making inter-cluster communication essential for achieving the overall objectives of the SoC; its efficiency directly impacts performance metrics. In this article, we present a communication mechanism that integrates message passing and shared memory between clusters. This mechanism encompasses both hardware and software components, accommodates variable message lengths, and ensures low latency. Verification conducted on Palladium and HAPS simulation platforms demonstrates that with 256-byte messages under FreeRTOS conditions, the average delay is 4900 clock cycles between ARM clusters, approximately 4700 clock cycles between ARM and RISC-V clusters, and around 4600 clock cycles within RISC-V clusters. Compared to existing open-source communication mechanisms for heterogeneous clusters, our proposed solution significantly reduces inter-cluster delay.