Performance Analysis for Electrical Noise Capabilities of TFET Configuration Topologies for Low Power Application

Tunnel field effect transistors (TFET) have become a viable alternative to classic CMOS due to their advantages, such as substantially decreased leakage current and steeper sub-threshold slope. The paper overviews several electrical noises that might arise in a fundamental TFET device. The presence of diverse noise sources in TFET, like random telegraph noise (RTN), flicker noise, shot noise, etc., has low/high-frequency noise that affects performance across different frequency bands. A different prototype with analytical capability has been created to investigate the alteration in electrostatic potential caused by a charged trap in the oxide of the gate of TFET by changing the materials. III-V materials like $\text{Ge} / \text{Si}, \text{GaAsSb} / \text{InGaAs}$, etc., hetero-junction TFET have been analyzed to compare the Gaussian trap; a uniform trap yields a higher Ion to Ioff ratio and lower subthreshold swing. The present research also investigates the influence of electrical noise on the efficiency of different TFET configurations. This study also compares five TFET structures: Ge-based Optimized work, SiGe-S-NW-TFET, Si based nanotube TFET, Si/SiGe HTG-TFET, and Ge-Source vTFET. The Ge-based TFET achieves the highest Ion of $80.9 \mu \text{A} / \mu \text{m}$ at $\text{V}_{\text{GS}}$ is 0.55 V, while the Ge-Source vTFET exhibits the lowest SS of $21.2 \text{mV} / \text{dec}$, highlighting their potential for low-power applications.