Demonstration of Low-Power Three-Dimensional CMOS Inverters Based on Si p-Tunnel FET and ITO n-FET

In this work, low-power CMOS inverter and 5-stage ring oscillator (RO) are demonstrated based on heterogeneous 3D integration of vertically stacked FEOL p-type silicon tunnel FET (TFET) and BEOL n-type indium-tin-oxide (ITO) FET. Owing to the low off-state current of both p-type and n-type FET, our ITO/TFET heterogeneous 3D integrated CMOS inverters show a low static power of 4.83 pW at V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> = 1 V and a high voltage gain of 522 V/V at V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> = 2.5 V, among the best values in reported amorphous oxide semiconductors (AOS) CMOS devices. Meanwhile, we also verified the functionality of logic circuits including 4T-SRAM cell and 5-stage RO based on our ITO/TFET heterogeneous 3D integrated CMOS inverters, and our 5-stage RO achieved a low propagation delay of 30 ns/stage, which is also the lowest value among AOS and TFET related CMOS devices.