A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique
A fractional-N LC oscillator-based PLL with a 1/4 quantization noise (QN) range reduction technique is proposed. Simple open loop delay cells are used to generate 4-phase clocks and reduce the QN by a factor of 4 while the mismatches of the 4 phases are calibrated and covered by a single DTC. Designed in 40-nm CMOS process, the proposed PLL achieves 159-fs RMSjitter with 2.6-mW power consumption, leading to -251.8-dB FoM.
Authors
- Gaofeng Jin (ORCID: https://orcid.org/0009-0001-8723-199X)
- Xiang Gao (ORCID: https://orcid.org/0009-0002-8627-3247)
- Hanli Liu (ORCID: https://orcid.org/0000-0002-0420-4284)
- Yan Chen (ORCID: https://orcid.org/0000-0003-0043-4469)
- Fei Feng
Institutions
- Zhejiang University (CN)
Publication Details
- Journal
- IEEE Solid-State Circuits Letters
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1109/lssc.2025.3528005
- Citations
- 4
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 2.92
Funders
- National Key Research and Development Program of China