A CMOS Linear Low-Noise Amplifier Using Transformer-Based Second-Harmonic Trap

This letter presents second-harmonic termination techniques for inductively source-degenerated cascode CMOS low-noise amplifiers (LNAs) with a transformer (TF)-based harmonic network. The proposed harmonic trap circuit terminates the second-order distortion generated in the common-source stage of the cascode structure, thereby improving the linearity of the LNA. In a transformed-based harmonic trap circuit, the primary inductor of the TF is used as the source-degenerated inductor for fundamental frequency gain and noise matching, and the secondary inductor along with an additional capacitor is used to terminate the second-harmonic frequency through <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$</tex-math> </inline-formula> resonance. The LNA is implemented using a 90-nm CMOS process and includes on-chip electrostatic discharge (ESD) protection circuits, making it suitable for commercialization. The fabricated LNA achieves a small signal gain of 18.48 dB, a noise figure (NF) of 1.1 dB, and an third input intercept point (IIP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{3}}$</tex-math> </inline-formula> ) performance of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 5.9 dBm at 2.62 GHz. The chip has an area of 416 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 879 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{2}}$</tex-math> </inline-formula> excluding the guard-ring layer, and it consumes 11.76 mW of power at a supply voltage of 1.2 V.

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Publication Details

Journal
IEEE Microwave and Wireless Technology Letters
Published
2025-01-10
DOI
https://doi.org/10.1109/lmwt.2024.3522299
Citations
3
Primary Topic
Electrostatic Discharge in Electronics
Type
article
Field-Weighted Citation Impact
2.19
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article

A CMOS Linear Low-Noise Amplifier Using Transformer-Based Second-Harmonic Trap

I.J. Kim, Min-Su Kim
3 citations
IEEE Microwave and Wireless Technology Letters
Electrostatic Discharge in Electronics
2.19
article

A CMOS Linear Low-Noise Amplifier Using Transformer-Based Second-Harmonic Trap

I.J. Kim, Min-Su Kim
article en
3 citations

Abstract

This letter presents second-harmonic termination techniques for inductively source-degenerated cascode CMOS low-noise amplifiers (LNAs) with a transformer (TF)-based harmonic network. The proposed harmonic trap circuit terminates the second-order distortion generated in the common-source stage of the cascode structure, thereby improving the linearity of the LNA. In a transformed-based harmonic trap circuit, the primary inductor of the TF is used as the source-degenerated inductor for fundamental frequency gain and noise matching, and the secondary inductor along with an additional capacitor is used to terminate the second-harmonic frequency through <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$</tex-math> </inline-formula> resonance. The LNA is implemented using a 90-nm CMOS process and includes on-chip electrostatic discharge (ESD) protection circuits, making it suitable for commercialization. The fabricated LNA achieves a small signal gain of 18.48 dB, a noise figure (NF) of 1.1 dB, and an third input intercept point (IIP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{3}}$</tex-math> </inline-formula> ) performance of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 5.9 dBm at 2.62 GHz. The chip has an area of 416 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 879 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{2}}$</tex-math> </inline-formula> excluding the guard-ring layer, and it consumes 11.76 mW of power at a supply voltage of 1.2 V.

IEEE Microwave and Wireless Technology LettersVol. 35(3)
Mokpo National University (KR)
Affordable and clean energy
Openalex Percentile: Top 14%
Electrostatic Discharge in Electronics
2.19
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