Research on Custom Algorithms and Hardware Accelerators Based on RISC-V Vector Extensions and Image Processing

RISC-V is an open, modular instruction set architecture (ISA) that has gained increasing adoption in fields such as image processing, machine vision, and deep learning inference due to its scalability and flexibility. This paper provides a comprehensive review of the latest research on RISC-V, with a focus on its vector extensions, custom instruction set optimizations, and the design and implementation of related hardware accelerators. The study employs a hardware-software co-optimization approach, featuring the design of a lightweight convolutional neural network (CSANet) and an artificial intelligence image signal processing (AI-ISP) accelerator to enhance image construction and inference efficiency. The experimental methods include performance evaluations based on FPGA hardware platforms, with a quantitative analysis of computational bottlenecks in the CSANet inference process, optimizing convolution operations and data flow handling. This research provides comprehensive technical support for the application of RISC-V in high-efficiency image processing and deep learning inference, especially in low-power and edge-computing scenarios.