Systematic Analysis on Performance Optimization of Tree Multipliers

The microprocessor chip is the core technology of the computer industry, and the multiplier is an important computing unit of the microprocessor. Its computing speed and area performances determine the performance of the microprocessor, and its structure determines whether it is easy to implement. Tree multipliers are widely used due to their superior performance. This article analyzes and compares the performance of several typical tree structures, including Wallace tree, Dadda tree, ZM tree, and OS tree, and compares various performance optimization methods, such as optimizing compressor structure, optimizing tree structure, and using PPA. This article found that the Wallace tree and Dadda tree have the fastest speed, but their irregular structures are not conducive to implementation. ZM tree and OS tree are two types of delay balancing trees with regular structures, but sacrifice speed and area performances. The optimization of compressor structure and tree structure, as well as the use of PPA, have reduced latency, but may lead to an increase in area. This article summarizes the current development of tree multipliers and has high reference value in future research.