Development of a 10-bit ultra-low power SAR ADC with programmable threshold in 130 nm CMOS technology

Abstract The design and simulation results of an ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in CMOS 130 nm technology are presented. This ADC is an extension of an experimentally verified 10-bit SAR ADC (INL, DNL < 0.5 LSB, ENOB > 9.5), working up to 50 MSps and consuming 680 μW at 40 MSps. The goal of the present work was to add a programmable threshold for the processed input signal, to stop the conversion and thus greatly reduce power consumption in case the signal is below the threshold. The new ADC works up to around 40 MSps and consumes around 350 μW at 40 MSps for low particle occupancy.