Design and optimization of multiplier for computer signal processing

The multiplier, serving as the fundamental construct for arithmetic operations within computing systems, wields a significant influence in the domain of modern electronic technology. This paper describes the definition, components and working principle of the multiplier, illustrates the hypotheses pertinent to the optimization and enhancement of the multiplier, conducting detailed simulations and analyses of these postulates, presents designing and implementing a low-power, high-speed 4x4 bit multiplier using TSMC 0.18 um CMOS technology. The design employs a modified column bypassing technique to minimise switching power activity and optimise power consumption and speed and delineates the concrete realization of the hypothesis previously mentioned. The final multiplier layout is optimised for reduced area and delay, achieving a layout area of 9398 um² and a post-layout delay of approximately 1.3422 ns. The result demonstrates the effectiveness of the modified column bypassing technique in achieving a balanced trade-of between power consumption and speed in multiplier design.