Multiplier optimization and application analysis

Multiplier is realized by the use of basic knowledge in the field of digital circuits. At present, the development of digital circuits has progressed from the past era of electronic tubes and other times to the era of integrated circuits, so in the case of the basic principle of multiplier unchanged, we need to explore more ways to realize multiplier. To expand the application range of multiplier, fit more circuit, used in different disciplines and fields. In this paper, using the knowledge of CMOS technology, BOOTH encoder algorithm and column bypass technology are combined to innovate the layout adjustment of multiplier, and the method of reducing energy consumption and delay of multiplier is realized. Including verifies basic electronic components (inverter, and gate, not gate, or gate), validation of a half adder and full adder, realized in the layout area of 9398 square micrometres, delay in 1.3422 ns. It proves that the innovation of the layout can improve the power consumption of the multiplier. Help multiplier used in more need under the condition of low power consumption and high efficiency, expand the application category of multiplier.