16-bit multi-cycle CPU based on RISC instruction set

This paper presents the design and implementation of a low-end CPU optimized for IoT applications. Low-end CPUs are critical in IoT and embedded systems for their power efficiency and cost-effectiveness. Our research focuses on key design strategies such as power optimization, RISC architecture enhancements, and CPU-FPGA integration for hardware acceleration. Specifically, this paper discusses various techniques including dynamic voltage and frequency scaling (DVFS), sub-threshold voltage operation, and body biasing to minimize power consumption. This paper discusses various techniques including dynamic voltage and frequency scaling (DVFS), sub-threshold voltage operation, and body biasing to minimize power consumption. Additionally, this paper explores the combination of CPUs with FPGAs to leverage their complementary strengths. Experimental results are presented from an FPGA implementation of the designed CPU, which successfully runs various functions including a running lights demonstration. These results validate the practical application and effectiveness of the design. Our findings contribute to advancing low-end CPU technology, meeting the market demand for efficient and low-power processors.