IMPLEMENTAÇÃO DA OPERAÇÃO DE DIVISÃO EM UMA UNIDADE DE PONTO FLUTUANTE DE 32 BITS BASEADA NO PADRÃO IEEE 754 EM VERILOG

A Floating-Point Unit (FPU) is an essential component of a computer processor responsible for performing arithmetic operations on floating point numbers, following the specifications of the IEEE 754 standard. The UPF consists of a series of circuits and logic designed to handle the representation, manipulation and calculations of floating-point numbers. It is responsible for converting the floating-point numbers into proper internal representations, performing the necessary mathematical operations and providing the result in the correct format. This work presents the implementation of a 32-bit UPF based on the IEEE 754 standard, using the Verilog language with the objective of designing and simulating the unit during the implementation of the arithmetic operation of division. The division functional unit was implemented in Verilog language using the EDA Playground platform. Eleven test cases involving situations that can happen in the result of the operation such as: overflow, underflow and exceptions (NaN, infinity) were simulated. The results presented by the simulation in the eleven test cases were those expected for this type of operation with floating point. Approximations occur due to rounding when dividing the mantissas, as the result of this operation must be represented in 23 bits. Another approximation is since the operands arrive at the division unit converted into binary and most floating-point values require an infinite number of bits.