Research on ARINC 429 data validity check algorithm based on FPGA implementation

ARINC 429 bus has large amounts of applications in civil aircraft multi-electronic systems. During the communication nets of avionics and other airborne systems, multi-redundancy architectures are established for the purpose of high-reliability. For a single device that receives ARINC 429 data, it is complicated to accurately identify the validity of continuous buffered data from various transmitting sources. In this paper, a typical ARINC 429 data validity check issue is presented; subsequently, based on the ZYNQ series FPGA platform, the ARINC 429 hardware IP core at the PL side is built, and the ARINC 429 bus sending/parsing algorithm's code is written at the PS side to reproduce the problem; finally, the problem is analyzed, and the improved validity check algorithm is simulated and physically verified on the FPGA, that potentially promotes the reliability of ARINC 429 bus data validity check on civil aircraft.