Energy-efficient Multiplier Design Through Approximate Computing: Current Trends and Future Prospects

Approximate Computing can be effectively applied in error-tolerant applications in order to improve the energy efficiency of the circuits. Arithmetic units such as adders and multipliers are the core components in many embedded devices and hardware accelerators. In particular, multipliers have a significant influence on the performance and power characteristics of the system where they are inserted. As a result, approximate multiplier design has become an important research subject in recent years. This work discusses the state-of-the-art on the use of approximate computing to design energy-efficient multipliers. We observe that most of the proposed approximate multipliers rely on approximations in the partial product reduction, mainly exploiting approximate compressors or approximate adders. In addition, there are only few works targeting neural networks, which demonstrates that there is room for explore an approximate multiplier design in this application.The set of information provided in this paper allows to identify gaps in the literature and possibilities for new research on the design of low-power multipliers.