Bulk cum Quasi-Floating Gate Driven Current Mirror OTA using FVF and Double Recycling Structure with High Capacitive Load Drive Ability

This paper presents a double recycling current mirror OTA which used quasi floating gate cum bulk-driven input pair to ensure low-voltage operation with enhanced voltage gain, gain bandwidth (GBW) and slew rates (SRs). The proposed OTA replaced the tail transistor of the conventional V-I converter by two flipped voltage followers and used partial positive feedback (PPF) to further enhance its transconductance. The proposed circuit has been simulated in standard 180 nm n-tub bulk CMOS process technology using ± 0.25 V dual DC power supplies. The simulation results show high DC gain of 80 dB, GBW of 51.3 kHz utilizing power budget of 56.4 nW for load capacitor CL of 15 pF. This OTA ensured high common mode rejection ratio (CMRR) of 88.2 dB, and positive and negative power supply rejection ratios PSRR+ and PSRR− of 80.6 dB and 89 dB, respectively. The proposed OTA’s performances are validated under device process corner, voltage, temperature variation effects. Its layout vs post layout results showed good degree of matching. It has been employed for designing of biquadratic filter and three-phase oscillator to show it usability.

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Publication Details

Journal
Journal of Integrated Circuits and Systems
Published
2024-12-23
DOI
https://doi.org/10.29292/jics.v19i3.808
Primary Topic
Semiconductor materials and devices
Type
article
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article

Bulk cum Quasi-Floating Gate Driven Current Mirror OTA using FVF and Double Recycling Structure with High Capacitive Load Drive Ability

Tripurari Sharan, Anil Kumar Gautam
Journal of Integrated Circuits and Systems
Semiconductor materials and devices
article

Bulk cum Quasi-Floating Gate Driven Current Mirror OTA using FVF and Double Recycling Structure with High Capacitive Load Drive Ability

Tripurari Sharan, Anil Kumar Gautam
article en

Abstract

This paper presents a double recycling current mirror OTA which used quasi floating gate cum bulk-driven input pair to ensure low-voltage operation with enhanced voltage gain, gain bandwidth (GBW) and slew rates (SRs). The proposed OTA replaced the tail transistor of the conventional V-I converter by two flipped voltage followers and used partial positive feedback (PPF) to further enhance its transconductance. The proposed circuit has been simulated in standard 180 nm n-tub bulk CMOS process technology using ± 0.25 V dual DC power supplies. The simulation results show high DC gain of 80 dB, GBW of 51.3 kHz utilizing power budget of 56.4 nW for load capacitor CL of 15 pF. This OTA ensured high common mode rejection ratio (CMRR) of 88.2 dB, and positive and negative power supply rejection ratios PSRR+ and PSRR− of 80.6 dB and 89 dB, respectively. The proposed OTA’s performances are validated under device process corner, voltage, temperature variation effects. Its layout vs post layout results showed good degree of matching. It has been employed for designing of biquadratic filter and three-phase oscillator to show it usability.

Journal of Integrated Circuits and SystemsVol. 19(3)
North Eastern Regional Institute of Science and Technology (IN)
Openalex Percentile: Top 77%
Semiconductor materials and devices
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