Investigation of hardware testing utilizing standard 4-D convolution and optimized deep convolution formulas

The purpose of this study is to explore the application and performance of standard four-dimensional convolution and optimized deep convolution formulas in hardware testing. With the increasing use of convolutional neural networks (CNNs) in fields such as image and video processing, the challenge lies in completing these tasks efficiently on resource-constrained hardware platforms. This study uses a field programmable gate array (FPGA) as the test platform to compare the parameters, computation time, and power consumption of standard and deep convolutions under varying hardware conditions. Results indicate that deep convolution reduces memory usage by 90%, computation time by 70%, and power consumption by 50%. These findings demonstrate that deep convolution is particularly effective on low-power hardware platforms, such as mobile terminals and edge computing devices. In conclusion, deep convolutions offer an efficient, low-power solution for modern CNN hardware implementations.