Design of a debugger architecture for parallel programming in a heterogeneous environment from a co-design point of view

This paper presents the case of H/W and S/W co-design development for heterogeneous environments through the development of OpenCL debugger for RISC-V chip with accelerator function for parallel programming. The aim of the debugger development is to debug OpenCL applications running on the chip and host based on LLDB (Low-Level Debugger). The chip consists of RISC-V cores, supports FP64 data types, is a matrix/vector arithmetic accelerator with new instructions, and includes a basic RISC-V debug subsystem. We performed a targeted analysis of the RISC-V debug subsystem for debugging OpenCL applications running on the device to derive device development requirements. We also designed the debugger architecture by analysing the programming execution model.