A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power

Performance optimization is a crucial aspect of enhancing the efficiency of electronic systems, and scaling is a primary method for achieving optimal performance while maintaining the integrity of system architecture. This paper introduces a novel algorithm for optimizing transistor sizing in static random-access memory (SRAM) to enhance speed, improve Static Noise Margin (SNM), and reduce leakage power consumption. The SRAM is designed using 45 nm technology and operates at a supply voltage of 1.2 V. To validate the algorithm's effectiveness, Monte Carlo simulations were conducted under varying process, voltage, and temperature conditions. The results demonstrate that read access times of 11.17 ps (HIGH) and 9.97 ps (LOW) and write access times of 12.00 ps (HIGH) and 17.00 ps (LOW). The measured SNM values for the read, write, and hold states were 328.2 mV, 453.7 mV, and 452.3 mV, respectively. The inclusion of precharge and write driver circuits allows for a compact SRAM layout, occupying 9.79 μm², with the SRAM cell itself occupying 4.1 μm². Furthermore, the proposed SRAM design exhibits a low leakage power consumption of 1.64 pW, demonstrating the efficiency and performance benefits of the optimized transistor sizing approach.