A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor
This letter describes a Delta-Sigma ADC based Power-Side-Channel-Attack Sensor. Use of 64 sampling capacitors allows the use of over-sampling architecture even with a decoupling capacitor connected to the power supply. The LDO with low-leakage S/H is used as a driver for the integrator’s amplifier to minimize the offset error. A differential conversion method utilizing Dual-Integrate capacitors (CAPs) provides signal processing to compensate for drift due to supply voltage (VDD) variations. The prototype sensor chip fabricated in 65nm CMOS has a worst-case detection accuracy of 98.7%, including VDD variations, for an insertion resistance >= 0.25Ω and a power consumption of 50uW at 1.0V operation.
Authors
- Avinash L. Varna (ORCID: https://orcid.org/0009-0009-4189-5860)
- Sigang Ryu (ORCID: https://orcid.org/0000-0001-5307-8117)
- S. KONNO (ORCID: https://orcid.org/0000-0003-3125-3580)
- Sanu Mathew (ORCID: https://orcid.org/0000-0003-1344-7533)
- Anupam Golder (ORCID: https://orcid.org/0000-0003-0725-1593)
- Arijit Raychowdhury (ORCID: https://orcid.org/0000-0001-8391-0576)
- Zachary J. Ellis (ORCID: https://orcid.org/0009-0004-6381-6362)
- Daniel Dinu
Institutions
- Georgia Institute of Technology (US)
- Intel (United States) (US)
- Asahi Kasei (Japan) (JP)
Publication Details
- Journal
- IEEE Solid-State Circuits Letters
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1109/lssc.2025.3527153
- Citations
- 1
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.73
Funders
- Semiconductor Research Corporation