A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor

This letter describes a Delta-Sigma ADC based Power-Side-Channel-Attack Sensor. Use of 64 sampling capacitors allows the use of over-sampling architecture even with a decoupling capacitor connected to the power supply. The LDO with low-leakage S/H is used as a driver for the integrator’s amplifier to minimize the offset error. A differential conversion method utilizing Dual-Integrate capacitors (CAPs) provides signal processing to compensate for drift due to supply voltage (VDD) variations. The prototype sensor chip fabricated in 65nm CMOS has a worst-case detection accuracy of 98.7%, including VDD variations, for an insertion resistance >= 0.25Ω and a power consumption of 50uW at 1.0V operation.

Authors

Institutions

Publication Details

Journal
IEEE Solid-State Circuits Letters
Published
2025-01-01
DOI
https://doi.org/10.1109/lssc.2025.3527153
Citations
1
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.73

Funders

Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor

Avinash L. Varna, Sigang Ryu, S. KONNO, Sanu Mathew et al.
1 citations
IEEE Solid-State Circuits Letters
Advanced Memory and Neural Computing
0.73
article

A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor

Avinash L. Varna, Sigang Ryu, S. KONNO, Sanu Mathew, Anupam Golder, Arijit Raychowdhury, Zachary J. Ellis, Daniel Dinu
article en
1 citations

Abstract

This letter describes a Delta-Sigma ADC based Power-Side-Channel-Attack Sensor. Use of 64 sampling capacitors allows the use of over-sampling architecture even with a decoupling capacitor connected to the power supply. The LDO with low-leakage S/H is used as a driver for the integrator’s amplifier to minimize the offset error. A differential conversion method utilizing Dual-Integrate capacitors (CAPs) provides signal processing to compensate for drift due to supply voltage (VDD) variations. The prototype sensor chip fabricated in 65nm CMOS has a worst-case detection accuracy of 98.7%, including VDD variations, for an insertion resistance >= 0.25Ω and a power consumption of 50uW at 1.0V operation.

IEEE Solid-State Circuits LettersVol. 8
Georgia Institute of Technology (US), Intel (United States) (US), Asahi Kasei (Japan) (JP)
Semiconductor Research Corporation
Affordable and clean energy
Openalex Percentile: Top 32%
Advanced Memory and Neural Computing
0.73
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor — Avinash L. Varna, Sigang Ryu, et al. · IEEE Solid-State Circuits Letters (2025) | TGRS Research Map | TGRS