Design of High-Speed Low-power SRAM Cell using FinFET in the Stack Method for Medical Applications

This research presents a high-speed, low-power Static Random-Access Memory (SRAM) cell design utilizing the Stack Method, tailored specifically for medical applications. The Stack architecture using Fin-FET technology is employed to effectively reduce power consumption and access delays during both write and read operations. The proposed SRAM cell achieves notable power efficiency, with a power consumption of 35.9 nanowatts (nW). The delays are also significantly reduced with the write time of 168.377 picoseconds (ps) and read time of 212.35 ps. The circuit has been simulated in the Cadence Virtuoso EDA tool. This design can be used in medical applications because of its efficient performance parameters.