Two-Stage Current Limiting Control Strategy for DC Solid-State Power Controller

This paper proposes a two-stage current limiting control strategy for DC Solid-State Power Controllers (SSPCs), aimed at addressing the challenges posed by inrush current and thermal stress during the rapid switching of large capacitive loads. In the resistor-based current limiting stage, a current-limiting resistor is utilized to suppress the inrush current, thereby protecting the system from instantaneous high current damage. In the gate voltage clamping current limiting stage, the gate voltage of the main-branch MOSFET is clamped to a given value, enabling rapid charging of the load capacitor. Throughout the limiting process, natural commutation occurs between the main branch and the current-limiting branch, resulting in a continuous variation of the SSPC's equivalent resistance. This effectively reduces secondary inrush current and fully utilizes the thermal capacity of the power devices. Experimental results show that the SSPC employing this strategy can switch on a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3300\mu \mathrm{F}$</tex> capacitive load within 10.1ms, with an initial inrush current of 191A and a secondary inrush current of less than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$76\mathrm{A}$</tex>, verifying the effectiveness and reliability of the proposed strategy.