A Superscalar Six-Stage Pipeline Neural Network Accelerator: Design and Implementation Based on FPGA

The growing need for efficient neural network inference in embedded systems has spurred the development of specialized hardware accelerators. This paper introduces the design and implementation of an FPGA-based Neural Processing Unit (NPU), optimized for high-performance neural network tasks. The NPU architecture integrates advanced features, including SIMD (Single Instruction, Multiple Data) support, an out-of-order execution system, and a six-stage pipeline, ensuring efficient processing. The NPU's RAM system manages both instruction and data storage, while 16-bit floating-point (FP16) computations balance precision with resource efficiency. On the software side, the NPU utilizes a custom instruction set, supported by a C language framework and a Python-based compiler. Detailed analyses of key modules, such as scalar and matrix operations, neural network inference, and RAM storage, are provided. Simulation tests, including handwritten digit recognition using the MNIST dataset, validate the NPU's functionality and performance, demonstrating its robust computational capabilities and efficiency. This study offers a novel and practical approach to achieving efficient neural network inference on FPGA, underscoring the NPU's superior performance in handling complex tasks.