Analysis of the implementation efficiency of digital signal processing systems on the technological platform SoC ZYNQ 7000

The subject of this paper is the analysis of DSP algorithm implementations based on HLS synthesis and SIMD instructions acceleration on the SoC hardware platform. The goal of this article is to analyze various FIR filter software and hardware implementations based on the technological platform SoC ZYNQ 7000 while obtaining metrics of hardware resource consumption, power efficiency, and execution performance. The tasks are as follows: determine the ways of implementing algorithms; choose the analysis criteria for multivariate experiment; implement algorithms using SIMD instructions on the ARM part of the given SoC; implement algorithms using High-Level Synthesis for the FPGA part; and measure and obtain the results for each signal topology. The used methods: High-Level Synthesis, optimization techniques based on vector instructions, and multivariate experiment analysis. The following results were obtained: for the given criteria and metrics. The FIR filter was implemented on the ZedBoard development platform with SoC ZYNQ 7000. The data were obtained from post-synthesis power analysis and dynamic SoC consumption using tools from Xilinx and Analog Devices. The corresponding IP blocks were implemented using High-Level Synthesis. The experiment was completed to obtain execution performance metrics. Conclusions. The scientific novelty of the obtained results is summarized as follows: the competitor analysis was performed for the set of implementations of the given algorithms deployed on the ZYNQ platform using both SIMD instructions and several HLS-based topologies for the FPGA-offload execution strategy. The analysis of the multivariate experiment was also completed for selected criteria, power consumption, filtering speed (inverse value – delay), and the amount of hardware costs as a percentage of the used resources.