Research on process-induced effect in 14-nm FinFET gate formation and digital unit optimization design

Abstract The advanced fin-shaped field-effect transistor (FinFET) technology offers higher integration density and stronger channel control capabilities, however, more complex process effects are also introduced which have significant influence on device performance. To address these issues, we complete a design-technology co-optimization (DTCO) focused on FinFET, including both process-induced effect during gate formation and corresponding digital unit optimization design. The 14 nm FinFET complementary metal oxide semiconductor (CMOS) technology is used to illustrate the sensitivity of transistor performance to process-induced effect, specifically the poly pitch effect (PPE) and cut poly effect (CPE). Predictive technology computer aided design (TCAD) simulations have been carried out to evaluate the transistor performance in advance. Based on the results, optimizations in digital unit design is proposed. Fall delay of the digital unit inverter is decreased by 0.7%, and the rise delay is decreased by 2.1%. For multiple selector (MUX2NV), the delay decreases by 4.64% for rise and 3.56% for drop, respectively.