A real-time JPEG image compression hardware design architecture

In technology 4.0, all data is put on the Cloud for transmission and processing. Images are one of the most important data and are quite large because they are created every day. Therefore, the increased demand for image storage and transmission urges scientists to research image compression methods to reduce the excess image data and it can solve the above problem. This paper presents the Field Programmable Gate Array (FPGA) hardware architecture of the JPEG image compression method (the world’s most popular image compression method) using FDCT numerically calculated Floating Point combined with Pipeline. The main goal of the proposed method is to increase the processing speed and compression performance of the image. The tests were performed on Red-Green-Blue (RGB) standard images. Evaluated by execution time, mean error value (MSE), top noise ratio (PSNR), and compression ratio (CR). This complete design is synthesized on the Vitex7-VC709 board with a frequency of 100.7 Mhz, throughput of 250 FPS, and power consumption of 2.401 Watts.