ChameSC: Virtualizing Superscalar Core of a SIMD Architecture for Vector Memory Access

In modern computing, the persistent issue of the memory wall significantly inhibits performance efficiency, especially in Single Instruction, Multiple Data (SIMD) architectures processing data-parallel workloads. Contemporary applications, including machine learning, data analytics, and computer vision, often feature complex chains of dependent, indirect, stride, and indexed vector memory accesses. These intricate access patterns place substantial pressure on vector memory units, leading to underutilization of SIMD resources and overall performance degradation. This study introduces ChameSC<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup><sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>A combination of Chameleon and Superscalar Core., a novel, adaptive SIMD architecture addressing the escalating memory wall issue. ChameSC exploits the typically idle memory units of the superscalar core during data-parallel workload execution by dynamically virtualizing the core to function as a precise data prefetcher, fetching data exactly as needed by the SIMD architecture in advance. The L1 cache of the superscalar core serves as a proactive cache to store prefetched data, which can be directly accessed by the vector memory unit. This strategic utilization of idle resources significantly enhances memory-level parallelism and effective memory bandwidth. Evaluations of ChameSC demonstrate substantial performance enhancements, achieving an average speedup of 34.3% compared to conventional SIMD architectures across a range of representative data-parallel applications with various memory access behaviors. Compared to state-of-the-art data prefetching techniques such as Berti and IPCP, ChameSC offers better performance without introducing extra storage overhead.