Pseudo-Sim: An Accurate Analytical Modeling Framework for Systolic Array Architectures

Array-based accelerators have emerged as powerful compute engines for meeting the immense computational de-mands of artificial intelligence (AI). However, current tools for optimizing their complex multidimensional hardware-software design space feature a strict tradeoff between accuracy and runtime. Here, we introduce Pseudo-Sim, a rapid and accurate methodology to simulate key system parameters including the number of compute clock cycles, off-chip DRAM accesses, and SRAM accesses. We validate the effectiveness of our tool by running it on the Resnet50V1.5 and BERT-Base neural networks for multiple hardware configurations and comparing results to those from a a cycle-accurate simulator. Pseudo-Sim achieves < 5% error in key parameters while reducing the runtime from tens of minutes to fractions of a second per layer (over <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10^{4}\times$</tex> speedup).