Modeling Communications in SoC and Co-simulation Analysis with IEEE 1666 SystemC

IEEE 1666 (SystemC) plays a vital role in system level design and verification of complex communication circuits along with several other modeling languages. It is capable of providing a powerful framework for modeling and simulating System on Chip (SoC) architectures, helping designers to explore system-level behaviour and optimise performance early in the development process. This paper carries out two primary investigations - first, it examines the differences in computation time while modeling circuits both simple and complex with Simulink and SystemC TDF (Timed Data Flow). The results show that SystemC TDF outpaces Simulink in terms of speed irrespective of the circuit complexity. The second investigation is a comparative study to analyse the ability of Matlab and Octave for co-simulation with SystemC. Co-simulation allows the integration of components in several domains along with high flexibility in system verification. The co-simulation flow starts with a sinusoidal source generated in Matlab which is used as an input source for a SystemC TDF module whose output is further post-processed in Matlab. In addition, similar investigations are done with Octave, using it for both post and pre-processing. The computational time in both cases are evaluated for each stages of the co-simulation flow and proves that Matlab is significantly faster than Octave in the investigated setups.