A Methodology for Fast and Efficient ML-Based Power Modeling

Power analysis is a key step in hardware (HW) development, particularly at the Register Transfer Level (RTL) stage where significant design modifications can still be made. As designs scale, power analysis requires increasingly larger simulation traces, sometimes reaching terabytes. This can take weeks or months to process, often making the analysis impractical. Power models are used to speed up this stage, but building them also requires large datasets, making the process slow. This work proposes a methodology to accelerate ML-based power modeling by training on a subset of the dataset, focusing on representative windows through clustering. Applied to a RISCV Rocket core and masked AES, our approach achieves up to 49 x speedup with minimal loss of accuracy, predicting power consumption with less than 5% error.