Dual-Axis ECC: Vertical and Horizontal Error Correction for Storage and Transfer Errors

DRAM technology has continually evolved to meet escalating demands for higher memory capacity and greater data bandwidth. This progression, however, has also led to increases in both storage and transfer errors, primarily due to the smaller transistors and higher transfer rates. To combat these errors, systems employ both Error Correcting Codes (ECC) and Cyclic Redundancy Check (CRC), despite their substantial performance and energy costs. This paper introduces a novel ECC, Dual-Axis ECC (DA-ECC), which provides unified protection against both storage and transfer errors. DA-ECC enhances traditional ECC approaches to correct one half-chipkill error, two DQ errors, or one transfer error on the Data Strobe (DQS) signal in × 8 DRAM chips. This comprehensive protection eliminates the need for additional CRC mechanisms. Our evaluations demonstrate that DA-ECC not only enhances system performance by up to 1.6% but also improves DRAM energy efficiency by up to 8.2% while providing a robust solution to the dual challenges of storage and transfer errors.