A 24GHz heterodyne CMOS receiver in 65nm technology

A 24GHz CMOS RF receiver for short range applications is developed in this paper. This paper presents the design of a heterodyne receiver and the results achieved. Heterodyne receivers are advantageous in eliminating DC offset problems, suppressing flicker noise and 2nd order non-linearity, due to the two-step down-conversion topology. The proposed RF IC includes a low-noise amplifier (LNA), two down-conversion mixers (one for lowering the working frequency to the first intermediate frequency (IF1) range (4.4GHz - 5.2GHz), and the other for lowering to the baseband frequency (IF2) range ( - 20kHz)), and two amplifiers for each IF for additional power gain. The main goal of achieving a high conversion gain and low noise are met, with results showing a conversion gain of 77dB (voltage gain of 98dB) and a noise figure of 6.39dB with a power consumption of 62.5mW.