Semiconductor Dry Etching Innovation in the Era of 3D Monolithic Integration

Two-dimensional scaling of integrated circuits was the backbone of Moore’s law for 50 years. Today, however, as feature sizes reach physical limits, new approaches are needed. Monolithic scaling in the third dimension is one of the solutions. NAND flash memory started to grow in the vertical direction in 2014 with just 24 layers of memory cells with 128 Gbit of storage. The fact that the industry is targeting 1000 layers only 10 years later is testament to the stunning success of vertical integration. One thousand layers will enable petabyte solid state drives by 2030. Cryogenic reactive ion etch (RIE) of high aspect ratio holes in silicon-based dielectrics is one of its enabling technologies. Logic and dynamic random access memory (DRAM) are also conquering the third dimension. The structures of these devices are very complicated and demand novel selective etching processes which can remove material in the lateral direction.