Design and Implementation of High-Speed Universal Asynchronous Receiver and Transmitter (UART)

The Universal Asynchronous Receiver and Transmitter (UART) are described, which is essentially a serial data transfer protocol used in digital circuit applications. The UART transmitter architecture has a baud rate generator, a parity generator, a transmitter finite state machine (FSM), and a parallel in serial out (PISO) register. The UART receiver is composed of a baud rate generator, a negative edge detector, a parity checker, a receiver Finite State Machine (FSM), and a serial in parallel out (SIPO) register. The transmitter and the receiver have the same baud rate generator; therefore, the transmitter/receiver baud rate is the same. The baud rate generator is the same as the frequency divider circuit. A UART transmitter data frame has 1 start bit, 8 transmit data bits, 1 parity bit, and 1 stop bit. The transmission rate of the transmitter and receiver is 4 Mbps using a 64 MHz system clock. Implementation, simulation and synthesis are done using Xilinx Vivado version 2018.2. The design is verified using a simulated waveform and synthesized on an FPGA Zed board. Keywords: Finite State Machine (FSM), Parallel in Serial out (PISO), Serial in Parallel out (SIPO), FPGA