Optimal Design of Vedic Multiplier for Computation in Memory Applications

The increasing demand for computational efficiency and power management in VLSI systems highlights the need for innovative architectural solutions. Traditional designs of-ten face challenges in balancing speed, power consumption, and area efficiency due to inefficiencies in data movement between processing units and memory. Computation in Memory (CIM) techniques address the memory wall problem, where data transfer limitations between processing and memory units hinder performance. CIM enables computations to occur directly within memory arrays, significantly reducing data movement and improving both speed and power efficiency. To address these issues, a novel architecture integrates CIM with a 16x16 Vedic Multiplier, incorporating a 2x2 Vedic Multiplier within 8T SRAM memory arrays and using latch-type sense amplifiers for in-memory computation. This integration reduces data movement, latency, and power consumption. Post-routing analysis further demonstrates a power decrease from 615µW to 595W. Detailed parasitic extraction and simulation using Standard Parasitic Exchange Format (SPEF) files reveal a 15% reduction in power consumption and a 9% reduction in slack compared to traditional multipliers. This CIM-based approach enhances computational efficiency and sets a robust foundation for future advancements in VLSI design, addressing critical challenges in modern high-performance computing systems.