Efficient Ring Counter Design Using Pre-Charged and Non-Pre-Charged TSPC D-Flipflops

This paper presents a comparative analysis of non-precharged and precharged True Single-Phase Clock (TSPC) D flip-flops for use in low-power, high-performance digital circuits. The study focuses on key performance parameters such as transistor count, setup time, hold time, clock-to-Q propagation delay, average power consumption, and power delay product (PDP). The precharged TSPC D flip-flop demonstrates significant improvements, requiring only 11 transistors compared to 12 in the non-precharged design and 24 in the transmission gate-based reference. The precharged TSPC shows a 59% improvement in setup time and a 14% reduction in clock-to-Q delay compared to its non-precharged counterpart, while delivering a 54.6% lower clock-to-Q delay and 92 % lower power consumption than the transmission gate-based flip-flop. The PDP also improved by 96.4% relative to the transmission gate-based flip-flop, highlighting the energy efficiency of the design. Further analysis conducted by implementing 4-bit ring counters using both the precharged and non-precharged TSPC D flip-flops showed that the precharged TSPC-based ring counter exhibited more consistent and lower clock-to-Q delays, achieving up to a 10.5% reduction in the maximum delay compared to the non-precharged version. To assess performance under varying conditions, clock-Q delays and power consumption were evaluated across different voltage levels (0.8V, 1.0V, and 1.2V), confirming the precharged TSPC's superior efficiency, especially at lower voltage levels. These findings highlight the advantages of the pre-charged TSPC D flip-flop in achieving high-speed, low-power digital circuits, making it a compelling choice for modern sequential logic design.