Design and Verification of Power Efficient Built-In Self-Test

In IC design, Built-In Self-Test (BIST) integrates testing capabilities into the device, eliminating external test equipment needs and enabling automatic chip testing. BIST is economical and effective for ensuring quality and reliability, offering benefits like expedited testing, lower production costs, improved dependability, higher manufacturing efficiency, and shorter test durations. The project aims to design essential blocks like the Linear Feedback Shift Register (LFSR) and Static RAM (SRAM) as Circuit Under Test (CUT) for comprehensive IC testing, create a Multiple input signature register (MISR) to identify incorrect sequences and validate golden signatures, and focus on identifying Single Stuck at Faults (SSAFs). Power optimization is a key component, targeting efficiency and cost reduction in testing processes. The reversible LFSR-based BIST design with clock gating shows 20% lower total power than the standard LFSR-based BIST. The design is synthesized and further processed through various steps of Physical design and Physical verification using Cadence Innovus Implementation System. Further efficiency gains can be achieved through advanced low-power design techniques and integrating machine learning for dynamic power management and adaptive testing.