Advanced SoC-Level Interrupt Verification Utilizing ARM GIC-700

As System on Chip (SoC) designs grow more complex, manual interrupt verification becomes impractical. This paper presents an advanced SoC-level interrupt verification methodology utilizing ARM Generic Interrupt Controller (GIC700), with the System Memory Management Unit (SMMU) for efficient handling of virtual and physical addresses. Leveraging SystemC and Universal Verification Methodology (UVM) phases for sequence management, and C language for register interactions, the framework ensures thorough, standardized interrupt verification in ARM core-based SoC designs. Key objectives include analyzing protocols such as Advanced eXtensible Interface (AXI), AXI Stream, and Coherent Hub Interface(CHI), and utilizing ARM GIC and SMMU functionalities for interrupt handling. A comprehensive testbench verifies interrupts at the SoC level and analyzes the interrupt flow. Additionally, TCL wave-script optimizes simulation dump time by enhancing waveform data management which reduces the run time from 9.2hrs to 3.9hrs. This paper aims to provide a robust, efficient framework for interrupt verification, ensuring reliable performance in advanced ARM core-based SoC designs.

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Publication Details

Published
2024-11-07
DOI
https://doi.org/10.1109/csitss64042.2024.10816713
Primary Topic
VLSI and Analog Circuit Testing
Type
article
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article

Advanced SoC-Level Interrupt Verification Utilizing ARM GIC-700

B S Kariyappa, V S Sudhanva
VLSI and Analog Circuit Testing
article

Advanced SoC-Level Interrupt Verification Utilizing ARM GIC-700

B S Kariyappa, V S Sudhanva
article en

Abstract

As System on Chip (SoC) designs grow more complex, manual interrupt verification becomes impractical. This paper presents an advanced SoC-level interrupt verification methodology utilizing ARM Generic Interrupt Controller (GIC700), with the System Memory Management Unit (SMMU) for efficient handling of virtual and physical addresses. Leveraging SystemC and Universal Verification Methodology (UVM) phases for sequence management, and C language for register interactions, the framework ensures thorough, standardized interrupt verification in ARM core-based SoC designs. Key objectives include analyzing protocols such as Advanced eXtensible Interface (AXI), AXI Stream, and Coherent Hub Interface(CHI), and utilizing ARM GIC and SMMU functionalities for interrupt handling. A comprehensive testbench verifies interrupts at the SoC level and analyzes the interrupt flow. Additionally, TCL wave-script optimizes simulation dump time by enhancing waveform data management which reduces the run time from 9.2hrs to 3.9hrs. This paper aims to provide a robust, efficient framework for interrupt verification, ensuring reliable performance in advanced ARM core-based SoC designs.

Openalex Percentile: Top 73%
VLSI and Analog Circuit Testing
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