$L_{g}=10$ nm Gate all Around Si Based Nanowire MOSFET for High Performance Computing

This paper analyses the DC characteristics and electrostatic behavior of a Gate All Around (GAA) Silicon-based Nanowire MOSFET with a gate length <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L_{g}=10$</tex> nm. The device demonstrates a drain current of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$7.6\times 10^{-5}\mathrm{A}/\text{mm}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{DS}=1.2$</tex> V for a gate-to-source voltage sweep between 0 to 1 V. The threshold voltage achieved for the 3D SiNW-based MOSFET is 2.5 V. In addition, the conduction band and valence band are characterized at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Y=1$</tex> nm, 2 nm, and 3 nm, respectively. The proposed structure exhibits a leakage current of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10 \times 10^{-10}$</tex> A/mm. Furthermore, it offers a subthreshold swing of 71 mV/dec. Additionally, Shockley-Read-Hall recombination and potential distribution are also considered. Therefore, the pro-posed GAA Si-based NW MOSFET is suitable for next-generation high-performance computing.