Design and Simulation of CMOS Fractional-N All-Digital Phase-Locked Loop (ADPLL)

A CMOS-based Charge-Pump PLL (CP-PLL) is designed and simulated using SPICE. A fractional-N All-Digital PLL (ADPLL) is designed using SystemVerilog and its VLSI layout is designed using a 35nm CMOS process and RTL-to-GDSII (logic-to-layout) synthesis. The CP-PLL simulations are contrasted to the ADPLL - the latter of which is subject to less undesirable effects such as low cutoff frequencies and RC delay. The approach presented shows how CMOS ADPLLs can be efficiently designed using RTL and logic-to-layout synthesis, to produce practical PLLs occupying a small die area, with a low power consumption, that can be implemented as part of a transceiver IC.