Static Timing Analysis of Modified 8 Bit Pipelined Multiplier with Carry Lookahead Adder Approach

An 8-bit multiplier employing a carry-look-ahead adder (CLA) with a modified pipelined architecture. The research underscores the complexity of multiplication operations, which integrate both addition and shifting processes, leading to longer execution times ranging between 2 to 8 cycles. The modified pipelined approach has given better yield of 2 percent utilisation factor and minimal power consumption of 0.081 W and propagation delay of 7. 783ns. The analysis helps Verilog to model and analyze the multiplier design, focusing on unsigned data. The modified pipelined approach aims to optimize the performance by breaking down the computation into stages, thereby allowing higher clock frequencies and reducing dynamic power consumption.