Design of Low-Power 10T Full Adder for Sustainable Computing

In the realm of digital circuit design, the quest for low-power solutions has garnered considerable attention because of the proliferation of battery-powered devices and the imperative to minimize energy consumption. This paper presents a novel approach for designing a low-power 10T full adder utilizing the Lector technique. The suggested design presents a comparison between 9T and 10T circuits, leverages the advantages of the Lector technique, which employs dynamic node isolation to reduce leakage current and dynamic power dissipation. By carefully optimizing transistor sizing and circuit topology, the proposed 10T full adder achieves a balance between power efficiency and performance. This research proposes a novel full adder design that reduces power consumption by 4% compared to conventional implementations. Simulation results confirm its effectiveness in achieving significant power savings while maintaining acceptable speed and area overhead. Our approach enhances energy efficiency in digital circuits, making it suitable for low-power applications.